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YDA144
D- 4N
STEREO 2.1W Non-Clip DIGITAL AUDIO POWER AMPLIFIER Overview
YDA144 (D-4N) is a digital audio power amplifier IC with maximum output of 2.1W (RL=4)x2ch. YDA144 has a "Pure Pulse Direct Speaker Drive Circuit" which directly drives speakers while reducing distortion of pulse output signal and reducing noise on the signal, and realizes the highest standard low distortion rate characteristics and low noise characteristics among digital amplifier ICs for mobile use. In addition, circuit design with fewer external parts can be made depend on the condition of use because corresponds to filter less. The YDA144 features Yamaha original non-clip output control function which detects output signal clip due to the over level input signal and suppress the output signal clip automatically. Also the non-clip output control function can adapt the output clip caused by power supply voltage down with battery. This is the difference from the traditional AGC (Auto Gain Control) or ALC (Auto Level Control) circuit. Attack time and release time can be freely set by external resistances or capacitances. The independent power-down function for L channel and R channel minimizes consumption current at standby. As for protection function, overcurrent protection function for speaker output terminal, overtemperatue protection function for inside of the device, and low supply voltage malfunction preventing function are prepared.
Features
Maximum output 2.1 Wx2ch (VDDP=VDDA=5.0V, RL=4, THD+N=10%) 0.75 Wx2ch (VDDP=VDDA=3.6V, RL=8, THD+N=10%) Distortion Rate (THD+N) 0.03 % (VDDP=VDDA=3.6V, RL=8, Po=0.4W, 1kHz) Residual Noise 40Vrms (VDDP=VDDA=3.6V, Av=12dB) Efficiency 84 % (VDDP=VDDA=3.6V, RL=8, Po=600mW) 78 % (VDDP=VDDA=3.6V, RL=8, Po=100mW) S/N Ratio 95dB (VDDP=VDDA=3.6V, Av=12dB) Channel separation 95dB (VDDP=VDDA=3.6V, RL=8, Av=18dB, 1kHz) Over-current Protection function Thermal Protection function Low voltage Malfunction Prevention function 2ch independent power-down control function Power-down High speed Recovery function Package Lead-free 16-ball WLCSP (YDA144-WZ) Lead-free 20-pin QFN (YDA144-QZ)
YDA144 CATALOG CATALOG No.:LSI-4DA144A30 2006.11
YDA144
Terminal configuration
<16-ball WLCSP Top View>
<20-pin QFN Top View>
2
YDA144
Terminal function
WLCSP16
No. Name I/O Protection circuit composition Function A1 A INL+ PN Positive input terminal (differential +) Lch A2 Power PVDD Power supply for output A3 O OUTL+ Positive output terminal (differential +) Lch A4 O OUTLNegative output terminal (differential -) Lch B1 A INLPN Negative input terminal (differential -) Lch B2 I/O NCRC PN Non-Clip control terminal B3 I /SDR N Shut-down terminal for Rch B4 I /SDL N Shut-down terminal for Lch C1 A INRPN Negative input terminal (differential -) Rch C2 I G0 N Gain setting terminal C3 GND AGND GND for analog circuits C4 GND PGND GND for output D1 A INR+ PN Positive input terminal (differential +) Rch D2 Power AVDD Power supply for analog circuits D3 O OUTR+ Positive output terminal (differential +) Rch D4 O OUTRNegative output terminal (differential -) Rch (Note) I: Input terminal O: Output terminal A: Analog terminal When a voltage that is bigger than the AVDD potential is impressed to the terminal of PN (protection circuit is composed of PMOS and NMOS), the leakage current flows through the protection circuit of PMOS.
QFN20
No. Name I/O Protection circuit composition Function 1 I/O Non-Clip control terminal NCRC PN 2 O Positive output terminal (differential +) Lch OUTL+ 3 Power Power supply for output PVDD 4 GND GND for output PGND 5 O Negative output terminal (differential -) Lch OUTL6 Non connection or connect to AGND NC 7 I Shut-down terminal for Lch /SDL N 8 I Shut-down terminal for Rch /SDR N 9 Power Power supply for analog circuits AVDD 10 Non connection or connect to AGND NC 11 O Negative output terminal (differential -) Rch OUTR12 GND GND for output PGND 13 Power Power supply for output PVDD 14 O Positive output terminal (differential +) Rch OUTR+ 15 I Gain setting terminal G0 N 16 A Positive input terminal (differential +) Rch INR+ PN 17 A Negative output terminal (differential -) Rch INRPN 18 GND GND for analog circuits AGND 19 A Negative input terminal (differential -) Lch INLPN 20 A Positive input terminal (differential +) Lch INL+ PN (Note) I: Input terminal O: Output terminal A: Analog terminal When a voltage that is bigger than the AVDD potential is impressed to the terminal of PN (protection circuit is composed of PMOS and NMOS), the leakage current flows through the protection circuit of PMOS.
3
YDA144
Block diagram
4
YDA144
Description of operating functions
Digital Amplifier Function
YDA144 has digital amplifiers with analog and digital input, PWM pulse output, Maximum output of 2.1W(RL=4)x2ch. Distortion of PWM pulse output signal and noise of the signal is reduced by adopting "Pure Pulse Direct Speaker Drive Circuit" In addition, YDA144 has been designed so that high-efficiency can be maintained within an average power range (100mW or so) that is used for mobile terminal. First Stage Amplifier Gain Setting Function G0 terminal can set the Gain of YDA144. When Non-Clip function is disabled, the relation between G0 terminal setting and Gain is as follows. Digital Amplifier Gain Setting G0 Gain Input Impedance(ZIN) L 12dB 44k H 18dB 28k Note H and L indicates logic High and logic Low, respectively. Input Lch differential input signals to INL+ terminal and INL- terminal through DC-cut capacitors (CIN). For single ended operation, input the signal to INL+ pin through the DC-cut capacitor (CIN). At this time, INL- pin must be connected to AVSS pin through a capacitor (CREF: same value as CIN). As with Lch, connect input signals to Rch.
Differential input
Single input
In addition, positive (+) and negative (-) sides of differential input pins (INL+ and INL-, or INR+ and INR-), input pins of the unused channel side, should be connected to each other and connected to AVSS through a capacitor. Use a capacitor with the same capacitance (0.1F) as that of a DC-cut capacitor in the channel side being used.
Input terminal processing of unused channel side The lower cut-off frequency (fc) can be found from DC-cut capacitor (CIN) and input impedance (ZIN) as shown below. fc=1/(2 ZIN CIN) In order to reduce pop-noise, impedance in the differential input signal source is arranged. And, DC-cut capacitor (CIN) should be 0.1F or less.
5
YDA144
Non-Clip control Function
This is the function to control the output in order to obtain a maximum output level without distortion when an excessive input which causes clipping at the differential signal output is applied. That is, with the Non-Clip function, YDA144 lowers the Gain of the digital amplifier to an appropriate value so as not to cause the clipping at the differential signal output. And, YDA144 follows also to the clip of the output wave form due to the decrease in the power-supply voltage.

Connecting a resistor (Rex) and a capacitor (Cex) to NCRC terminal can set Attack Time and Release Time of the Non-Clip control. A temperature compensation type ceramic capacitor is recommended as capacitor (Cex).
The Attack time is a time interval until gain falls to target attenuation gain -3dB with a big signal input enough. And, the Release Time is a time from target attenuation gain to not working of Non-Clip. With the target attenuation gain of 10dB, the Attack Time and Release Time is as can above Table.
6
YDA144
Resistor(Rex), Capacitor(Cex) and Attack Time, Release Time Rex(M) 1 4.7 1 Cex(F) 1 1 0.47 Attack Time(ms) 10 10 4.7 Release Time(s) 0.8 3.8 0.38 1 4.7 47 3.8
Non-Clip control function can be invalidated by the NCRC terminal assumption H level fixation (AVDD potential) or L level fixation (GND). In that case, the following differences exist by the state of the NCRC terminal.
Difference of operation by state of NCRC terminal when Non-Clip control function is OFF. NCRC terminal L level (GND) H level (AVDD potential) Current increase [mA] 0.2 (Maximum) 0 Start up wait time [sec] 0 3 Rex Cex Non-Clip function ON/OFF change in state of signal input. Change is possible. Change is prohibited.
Start up wait time: It means time until the signal input is permitted from Non-Clip function ON.
Protection Function
YDA144 has the following protection functions for the digital amplifier: Over-current Protection function, Thermal Protection function, and Low voltage Malfunction Prevention function. Over-current Protection function This is the function to establish the over-current protection mode when detecting a short circuit between YDA144 differential output pin and VSS, VDD, or another differential output. The function works independently for Lch and Rch. In the over current protection mode, the differential output pin becomes a high impedance state. Setting /SDR pin to a logic Low state can cancel the Rch over current protection mode. Likewise, when setting /SDL pin to a logic Low level, the over current protection mode applied to Lch can be cancelled. In addition, turning on the power again can cancel the over current protection mode applied to Lch and Rch. Thermal Protection function This is the function to establish the thermal protection mode when detecting excessive high temperature of YDA144 itself. In the thermal protection mode, the differential output pin becomes Weak Low state (a state grounded through high resistivity). And, when YDA144 gets out of such condition, the protection mode is cancelled. Low voltage Malfunction Prevention function This is the function to establish the low voltage protection mode when AVDD pin voltage becomes lower than the detection voltage (VUVLL) for the low voltage malfunction prevention and to cancel the protection mode when AVDD pin voltage becomes higher than the threshold voltage (VUVLH) for its deactivation. In the low voltage protection mode, the differential output pin becomes Weak Low state (a state grounded through high resistivity). YDA144 will start up within the start-up time (TSTUP) when the low voltage protection mode is cancelled.
7
YDA144
Power-down Function
This is the function to turn Rch into the power-down mode when setting /SDR terminal to a logic Low level and to turn Lch into the power-down mode when setting /SDL terminal to a logic Low level. The power-down mode stops all the functions and minimizes current consumption. At this time, the differential output signal becomes Weak Low state (a state grounded through high resistivity). YDA144 will start up within the start-up time (Tstup) when setting /SDR and /SDL terminals to a logic High state. Caution When using a device while Non-Clip function is ON, power down state of both channels is released and used. Please do not adjust the AVDD power supply voltage to less than 2V, when set to power down with the voltage impressed to the PVDD power supply terminal. Power up the PVDD supply voltage in conjunction with the AVDD regulation circuit when AVDD is generated by regulating PVDD. AVDD voltage should be within the range of 2VAVDDPVDD as shown in the following figure when the AVDD regulation circuit needs to be stopped by power supply management.
Example of measures for AVDD regulation circuit stop option Notes in example of the above-mentioned measures When a voltage is supplied to PVDD pin, decide a value of Rx so that the voltage at AVDD pin becomes a value within the range of 2VAVDDPVDD. A value of Rx is about 100k to 500k, because the power-down leakage current (AVDD current) of YDA144 is 0.1A typ. (2A max.@125C). And, when an LSI other than YDA144 is connected to the same regulator, decide a value of Rx in consideration of all leakage currents. The regulator output may increase up to the supply voltage level (=PVDD voltage) such as a battery when load current is zero. Please carefully check if any problem such as LSI's withstand voltage would occur when an LSI other than YDA144 is connected to the same regulator. This measure is effective only when a regulator whose output during a stop state becomes the high impedance state is used.
Pop noise reduction function
The Pop Noise Reduction Function works in the cases of Power-on, Power-off, Power-down on, and Power-down off. And, the pop-noise can be suppressed according to control the power down by the following procedure. /SDR and /SDL terminal are assumed to be H, after power-on. /SDR and /SDL terminal are assumed to be L, before Power-off.
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YDA144
Snubber Circuit and schottky barrier diode
It is necessary to connect the snubber circuit and schottky barrier diode with the output terminal to prevent IC destruction by the output short-circuit when using it on the following conditions. The constant and the circuit are as follows.
Power supply voltage range 2.7VPVDD4.5V 4.5VPVDD5.25V Load conditions RL=8 Wiring inductance4H RL=4 or 8 Snubber Circuit Between OUT*+ and OUT*Rs=1.5, Cs=330pF Between OUT*+ and OUT*Rs=1.5, Cs=680pF Schottky barrier diode Need less Between OUT** and PVDD
Recommended parts Schottky barrier diode: ROHM, RB161VA-20 Forward current surge peak = 5A or more, Average forward current = 1A or more, Forward voltage (IF=1A) = 0.38V or less
Snubber circuit and Schottky barrier diode
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YDA144
Application circuit examples
WLCSP16
Snubber circuit and schottky barrier diode are unnecessary (2.7VPVDD4.5V)
Snubber circuit and schottky barrier diode are necessary (4.5VPVDD)
When the IC is used at more than 4.5V power supply, use it with an additional capacitor of 10F or over between PVDD and GND. Place a bypass capacitor as close as possible to each power supply pin of the IC.
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YDA144
QFN20
Snubber circuit and schottky barrier diode are unnecessary (2.7VPVDD4.5V)
Snubber circuit and schottky barrier diode are necessary (4.5VPVDD)
When the IC is used at more than 4.5V power supply, use it with an additional capacitor of 10F or over between PVDD and GND. Place a bypass capacitor as close as possible to each power supply pin of the IC.
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YDA144
Cautions for Safety
Please observe the following restrictions to use YDA144 safely. The snubber circuit should be laid out within 3mm from the IC on the component side. The schottky barrier diode should be laid out within 3mm from the IC. Place a bypass capacitor, which is connected between PVDD and GND, together with a schottky barrier diode. And, when no schottky barrier diode is required, place it within 3mm from the IC. When a LC filter is used, consider the following. With a system of which an input signal in excess of a resonance frequency of a LC filter could be input, be sure to place a snubber circuit (insert 13+330ns at the LC filter output) after the LC filter to prevent an over-current condition. The purpose is to prevent an over-current from flowing because an impedance of the speaker increases at the resonance frequency. With a system of which a voltage at an input pin might exceed a supply voltage of VDDA/GND, use an external diode etc. to assure that the voltage does not exceed the absolute maximum rating.
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YDA144
Electrical Characteristic
Absolute Maximum Ratings
Item Symbol Min. Max. Unit Power supply terminal (PVDD) Voltage Range VDDP 0.3 6.0 V Power supply terminal (AVDD) Voltage Range VDDP 0.3 6.0 V Input terminal Voltage Range VSS0.6 VDDA0.6 V VIN (Analog input terminals: INL+,INL-,INR+,INR-) Input terminal Voltage Range VSS0.3 VDDA0.3 V VIN (Input terminals except the above-mentioned) Allowable dissipation (16WLCSP,Ta=25) PD25 2.0 W Allowable dissipation (16WLCSP,Ta=85) PD85 0.80 W Allowable dissipation (20QFN,Ta=25) PD25 1.56 W Allowable dissipation (20QFN,Ta=85) PD85 0.62 W Allowable dissipation (20QFN,Ta=25) PD25 3.63 W Allowable dissipation (20QFN,Ta=85) PD85 1.45 W Junction Temperature TJMAX 125 Storage Temperature TSTG 50 125 Note) Absolute Maximum Ratings is values which must not be exceeded to guarantee device reliability and life, and when using a device in excess even a moment, it may immediately cause damage to device or may significantly deteriorate its reliability With a system of which a voltage at an input pin might exceed a supply voltage of VDDA/GND, use an external diode to assure that the voltage does not exceed the absolute maximum rating. *1: ja=50.0/W, conditions: YDA144 evaluation board (4 layers), dead calm *2: ja=64.0/W, conditions: YDA144 evaluation board (2 layers, without through-hole), dead calm *3: ja=27.5/W, conditions: 4 layers, through-hole, copper foil 65m, dead calm
Recommended Operating Condition
Item Symbol Min. Power Supply Voltage(PVDD) VDDP 2.7 Power Supply Voltage(AVDD) VDDA 2.7 Operating Ambient Temperature Ta 40 Speaker Impedance (4.5V PVDD) RL 4 Speaker Impedance (2.7V PVDD 4.5V) RL 8 Note) Do not use under a condition other than the recommended operating conditions. PVDD AVDD (contain power supply start up) must be met. The rising time of PVDD and AVDD should be more than 1. Typ. 3.6 3.6 25 Max. 5.25 5.25 85 Unit V V
DC Characteristics (VSS=0V, VDDP= VDDA =2.7V to 5.25V, Ta=40C to 85C, unless otherwise specified)
Item AVDD power supply start-up threshold voltage AVDD power supply shut-down threshold voltage /SDL, /SDR, G0 terminal H level input voltage /SDL, /SDR, G0 terminal L level input voltage AVDD consumption current PVDD consumption current Consumption current in power-down mode AVDD + PVDD Symbol VUVLH VUVLL VIH VIL IDD IDD IPD 1.35 0.35 VDDA=3.6V, no load VDDP=3.6V, no load, no signal input /SDL=/SDR=Vss, Ta=25 6.0 2.0 0.1 Conditions Min. Typ. 2.2 2.0 Max. Unit V V V V mA mA A
AC characteristics (VSS=0V, VDDP= VDDA =2.7V to 5.25V, Ta=40C to 85C, unless otherwise specified)
Item Start-up time Input cut-off frequency Attack time Release time Carrier clock frequency Symbol TSTUP fc TAT TRL fPWM Conditions CIN =0.1F, Av=18dB VDDA=3.6V, g=10dB, Cex=1F, Rex=1M VDDA=3.6V, g=10dB, Cex=1F, Rex=1M Min. Typ. 3.5 57 10 0.8 1.0 Max. Unit ms Hz ms s MHz
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YDA144
Analog Characteristics
(VSS=0V, VDDP= VDDA =3.6V, RL=8, Ta=25C, Non-Clip function=OFF, no snubber circuit, no schottky barrier diode, unless otherwise specified) Item Maximum output Voltage Gain Symbol PO AV Conditions RL=4, f=1kHz,THD+N=10%, VDDP=VDDA=5V RL=8, f=1kHz,THD+N=10% G0=L G0=H Min. Typ. 2.1 0.75 12 18 0.03 40 95 95 85 84 78 20 3 1 Max. Unit W W dB dB % Vrms dB dB dB % % mV dB dB
Total Harmonic Distortion Rate THD+N RL=8, Po=0.4W, f=1kHz (BW:20kHz) Residual Noise (A-Filter) Signal /Noise Ratio (BW:20kHz A-Filter) Channel Separation Ratio Power supply rejection ratio Maximum Efficiency Output offset voltage Frequency characteristics N SNR CS Av=12dB Av=12dB 1kHz RL=8, Po=600mW RL=8, Po=100mW
PSRR 217Hz (to PVDD)
Vo fRES
CIN =0.1F, f=100Hz to 20kHz
Non-Clip Aa 10 maximum attenuation gain Note) All the values of analog characteristics were obtained by using our evaluation circumstance. Depending upon parts and pattern layout to use, characteristics may be changed. 8 or 4 resistor and 30H coil are used as an output load in order to obtain various digital amplifier characteristics.
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YDA144
Typical characteristics examples
VDDA=VDDP=5V: Gain=18dB, Snubber circuit and schottky barrier diode are added. VDDA=VDDP=3.6V: Gain=12dB, no Snubber circuit, no schottky barrier diode. (VSS=0V, Ta=25C, Non-Clip=OFF, unless otherwise specified)
Output vs THD+N WLCSP16 V DDA=V DDP=5V R L=4+30uH
100
Output vs THD+N WLCSP16 VDDA=V DDP=5V R L=8+30uH
100
10
10
THD+N [%]
THD+N [%]
1
1
0.1
0.1
0.01 0.0001
0.001
0.01
0.1
1
10
0.01 0.0001
0.001
0.01
0.1
1
10
Output [W]
Output [W]
Output vs THD+N WLCSP16 V DDA=V DDP=3.6V R L=8+30uH
100
10
THD+N [%]
1
0.1
0.01 0.0001
0.001
0.01
0.1
1
10
Output [W]
Output vs THD+N QFN20 V DDA=V DDP=5V R L=4+30uH
100
100
Output vs THD+N QFN20 V DDA=V DDP=5V R L=8+30uH
10
10
THD+N [%]
1
THD+N [%]
0.001 0.01 0.1 1 10
1
0.1
0.1
0.01 0.0001
0.01 0.0001
0.001
0.01
0.1
1
10
Output [W]
Output [W]
Output vs THD+N QFN20 V DDA=VDDP=3.6V R L=8+30uH
100
10
THD+N [%]
1
0.1
0.01 0.0001
0.001
0.01
0.1
1
10
Output [W]
15
YDA144
Frequency vs THD+N WLCSP16 V DDA=V DDP=5V R L=4+30uH
1
Frequency vs THD+N WLCSP16 V DDA=V DDP=5V R L=8+30uH
1
0.1
0.1
THD+N [%]
THD+N [%]
0.01
0.01
0.001 10 100 1000 10000 100000
0.001 10 100 1000 10000 100000
Frequency [Hz]
Frequency [Hz]
Frequency vs THD+N WLCSP16 V DDA=V DDP=3.6V RL=8+30uH
1
0.1
THD+N [%]
0.01 0.001 10 100 1000 10000 100000
Frequency [Hz]
1
Frequency vs THD+N QFN20 V DDA=V DDP=5V R L=4+30uH
Frequency vs THD+N QFN20 V DDA=V DDP=5V R L=8+30uH
1
0.1
0.1
THD+N [%]
0.01
THD+N [%]
0.01 0.001 10 100 1000 10000 100000 0.001 10 100 1000 10000 100000
Frequency [Hz]
Frequency [Hz]
Frequency vs THD+N QFN20 V DDA=V DDP=3.6V R L=8+30uH
1
0.1
THD+N [%]
0.01 0.001 10 100 1000 10000 100000
Frequency [Hz]
16
YDA144
Output vs Efficiency WLCSP16 V DDA=V DDP=5V R L=4+30uH Non-Clip=OFF
100 90 80 70
100 90 80 70
Output vs Efficiency WLCSP16 V DDA=V DDP=5V R L=8+30uH Non-Clip=OFF
Efficiency [%]
Efficiency [%]
60 50 40 30 20 10 0 0 500 1000 1500 2000 2500
60 50 40 30 20 10 0 0 200 400 600 800 1000 1200 1400 1600 1800
Output [mW]
Output [mW]
Output vs Efficiency WLCSP16 VDDA=VDDP=3.6V R L=8+30uH Non-Clip=OFF
100 90 80 70
Efficiency [%]
60 50 40 30 20 10 0 0 100 200 300 400 500 600 700 800 900
Output [mW]
Output vs Efficiency QFN20 V DDA=V DDP=5V R L=4+30uH Non-Clip=OFF
100 90 80 70
100 90 80 70
Output vs Efficiency QFN20 V DDA=V DDP=5V R L=8+30uH Non-Clip=OFF
Efficiency [%]
60 50 40 30 20 10 0 0 500 1000 1500 2000 2500 3000
Efficiency [%]
60 50 40 30 20 10 0 0 200 400 600 800 1000 1200 1400 1600 1800
Output [mW]
Output [mW]
Output vs Efficiency QFN20 V DDA=VDDP=3.6V R L=8+30uH Non-Clip=OFF
100 90 80 70
Efficiency [%]
60 50 40 30 20 10 0 0 100 200 300 400 500 600 700
Output [mW]
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YDA144
Power supply voltage vs Maximum output Gain=18dB Lch
3.00 RL=4+30uH Non-Clip=OFF RL=8+30uH Non-Clip=OFF RL=4+30uH Non-Clip=ON RL=8+30uH Non-Clip=ON
Power supply voltage vs Maximum output Gain=12dB Lch
2.50 RL=4+30uH Non-Clip=OFF RL=8+30uH Non-Clip=OFF RL=4+30uH Non-Clip=ON RL=8+30uH Non-Clip=ON
2.50
2.00
Maximum output [W]
2.00
Maximum output [W]
1.50
1.50
1.00
1.00
0.50
0.50
0.00 2.5 3 3.5 4 4.5 5 5.5
0.00 2.5 3 3.5 4 4.5 5
Power supply voltage [V]
Power supply voltage [V]
Frequency vs CS WLCSP16 V DDA=V DDP=5V R L=4+30uH Po=1230mW
0
0
Frequency vs CS WLCSP16 V DDA=VDDP=5V R L=8+30uH Po=770mW
-20
-20 -40
-40
CS [dB]
-60
CS [dB]
-60
-80
-80
-100
-100
-120
-120 10 100 1000 10000 100000
-140 10 100 1000 10000 100000
Frequency [Hz]
Frequency [Hz]
Frequency vs CS WLCSP16 V DDA=V DDP=3.6V R L=8+30uH Po=400mW
0
-20 -40
CS [dB]
-60
-80
-100 -120
-140 10 100 1000 10000 100000
Frequency [Hz]
18
YDA144
Frequency vs CS QFN20 V DDA=V DDP=5V R L=4+30uH Po=1220mW
0 0
Frequency vs CS QFN20 V DDA=VDDP=5V R L=8+30uH Po=770mW
-20
-20
-40
-40
CS [dB]
-60
CS [dB]
10 100 1000 10000 100000
-60
-80
-80
-100
-100
-120
-120 10 100 1000 10000 100000
Frequency [Hz]
Frequency [Hz]
Frequency vs CS QFN20 V DDA=V DDP=3.6V R L=8+30uH Po=400mW
0
-20 -40
CS [dB]
-60
-80
-100 -120
-140 10 100 1000 10000 100000
Frequency [Hz]
Frequency vs PSRR (to PVDD) WLCSP16 V DDA=V DDP=5V RL=4+30uH
0 -10 -20 -30 0 -10 -20 -30
Frequency vs PSRR (to PVDD) WLCSP16 V DDA=V DDP=5V R L=8+30uH
PSRR [dB]
-50 -60 -70 -80 -90 -100 10 100 1000 10000 100000
PSRR [dB]
-40
-40 -50 -60 -70 -80 -90 -100 10 100 1000 10000 100000
Frequency [Hz]
Frequency [Hz]
Frequency vs PSRR (to PVDD) WLCSP16 V DDA=V DDP=3.6V R L=8+30uH
0 -10 -20 -30
PSRR [dB]
-40 -50 -60 -70 -80 -90 -100 10 100 1000 10000 100000
Frequency [Hz]
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YDA144
Frequency vs PSRR (to PVDD) QFN20 V DDA=V DDP=5V R L=4+30uH
0 -10 -20 -30 0 -10 -20 -30
Frequency vs PSRR (to PVDD) QFN20 V DDA=V DDP=5V R L=8+30uH
PSRR [dB]
PSRR [dB]
-40 -50 -60 -70 -80 -90 -100 10 100 1000 10000 100000
-40 -50 -60 -70 -80 -90 -100 10 100 1000 10000 100000
Frequency [Hz]
Frequency [Hz]
Frequency vs PSRR (to PVDD) QFN20 VDDA=V DDP=3.6V R L=8+30uH
0 -10 -20 -30
PSRR [dB]
-40 -50 -60 -70 -80 -90 -100 10 100 1000 10000 100000
Frequency [Hz]
Input vs Output WLCSP16 V DDA=V DDP=5V R L=4+30uH Non-Clip=OFF
4 3.5 2 3 2.5 2 1.5 1 0.5 0.5 0 0.0001 0 0.0001 2.5
Input vs Output WLCSP16 V DDA=VDDP=5V R L=8+30uH Non-Clip=OFF
Output [W]
Output [W]
1.5
1
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Input [Vrms]
Input [Vrms]
Input vs Output WLCSP16 V DDA=V DDP=3.6 R L=8+30uH Non-Clip=OFF
1.2
1
0.8
Output [W]
0.6
0.4
0.2
0 0.0001
0.001
0.01
0.1
1
10
Input [Vrms]
20
YDA144
Input vs Output QFN20 V DDA=V DDP=5V R L=4+30uH Non-Clip=OFF
4 3.5 2 3 2.5 2 1.5 1 0.5 0.5 0 0.0001 0 0.0001 2.5
Input vs Output QFN20 V DDA=V DDP=5V R L=8+30uH Non-Clip=OFF
Output [W]
Output [W]
1.5
1
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Input [Vrms]
Input [Vrms]
Input vs Output QFN20 V DDA=VDDP=3.6V R L=8+30uH Non-Clip=OFF
1.2
1
0.8
Output [W]
0.6
0.4
0.2
0 0.0001
0.001
0.01
0.1
1
10
Input [Vrms]
Input vs Output WLCSP16 V DDA=V DDP=5V R L=4+30uH Non-Clip=ON
2.5
Input vs Output WLCSP16 V DDA=V DDP=5V R L=8+30uH Non-Clip=ON
1.6 1.4
2
1.2 1
Output [W]
Output [W]
1.5
0.8 0.6 0.4
1
0.5
0.2
0 0.0001
0.001
0.01
0.1
1
10
0 0.0001
0.001
0.01
0.1
1
10
Input [Vrms]
Input [Vrms]
Input vs Output WLCSP16 V DDA=V DDP=3.6V R L=8+30uH Non-Clip=ON
0.7
0.6
0.5
Output [W]
0.4 0.3
0.2
0.1
0 0.0001
0.001
0.01
0.1
1
10
Input [Vrms]
21
YDA144
Input vs Output QFN20 V DDA=V DDP=5V R L=4+30uH Non-Clip=ON
3 1.6 1.4 1.2 2 1 0.8 0.6 1 0.4 0.5 0.2 0 0.0001 0 0.0001
Input vs Output QFN20 V DDA=V DDP=5V R L=8+30uH Non-Clip=ON
2.5
Output [W]
1.5
Output [W]
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Input [Vrms]
Input [Vrms]
Input vs Output QFN20 V DDA=V DDA=3.6V R L=8+30uH Non-Clip=ON
0.7
0.6 0.5
Output [W]
0.4
0.3
0.2 0.1
0 0.0001
0.001
0.01
0.1
1
10
Input [Vrms]
22
YDA144
Package Outline
23
YDA144
24
YDA144
25
YDA144
Notice
The specifications of this product are subject to improvement changes without prior notice.

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